Pedestrian Detection Reference FPGA Design

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The following block diagram presents the reference FPGA design (controller) for the Pedestrian Detection which is used with the logiPD-LDW Development Platform. It is designed using Xylon logicBRICKS IP cores and prepared for use with the Xilinx® Spartan-6 FPGAs. The reference design is fully compatible with Xilinx Platform Studio (XPS) and the EDK implementation tools.

Reference FPGA design for Pedestrian Detection

The Pedestrian Detection Reference FPGA - An Example Implementation
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The logiBAYER Color Camera Sensor Bayer Decoder IP core captures, de-mosaics (Bayer pattern) and stores the input video image in external memory. The logiBAYER stores the image in two different formats: full megapixel camera resolution and half of that resolution.

The key IP core in the presented FPGA architecture is the logiPDET Pedestrian Detector IP core. The logiPDET works at a single scale, i.e. the classifier is trained to recognize pedestrian at a fixed size. Extension to multiple scales is given by inserting the core in a framework that provides it with a sequence of re-scaled versions of the same input frame. In this way it is possible to detect pedestrians moving in an arbitrary range of distance.

This multiscaling operation is performed by the logiCVC-ML Compact Multilayer Video Controller and the logiWIN Versatile Video Input IP cores. The logiCVC-ML fetches video images from the memory and streams it to the logiWIN IP core that integrates a video scaler. The video scaler streams scaled down video the logiPDET pedestrian detector. High level post-processing is implemented in software.

The final output image showing detected pedestrians is displayed by the second logiCVC-ML video controller IP core.

Xylon offers FPGA design services and can make design changes on request!

Xylon logicBRICKS IP cores for Pedestrian Detection in Automotive and Surveillance Systems

logiPDET Pedestrian Detector is an HOG/SVM-based pedestrian detection IP core developed for vision-based embedded applications. The algorithm follows a discriminative approach and combines a HOG-based descriptor and a SVM classifier.

The HOG (Histogram of Oriented Gradients) is a descriptor designed to encode pedestrian structure. The SVM (Support Vector Machine) is a non probabilistic binary linear classifier trained to recognize pedestrian’s size.

	The logiPDET core is sourced from Technology Partner eVS embedded Vision Systems Srl.

The presented FPGA SoC architecture can be changed in any feasible way to support the requirements of particular applications. Please contact Xylon if your application requires design changes.

Xylon logicBRICKS IP cores are compatible with Xilinx Platform Studio and the EDK tools. FPGA designers can setup logicBRICKS and Xilinx IP cores through GUI implementation tools, optimize feature sets and control the utilization of FPGA resources, and in a drag & drop fashion, implement Xilinx SoCs without hand coding.

Read More:
- Pedestrian Detection and Lane Departure Warning - Introduction
- Xylon logiPD-LDW Development Platform for Pedestrian Detection and Lane Departure Warning
- The logiPD-LDW Development Platform Package
- Reference logicBRICKS Design for Rear Looking Lane Departure Warning

Pedestrian Detection Reference FPGA Design

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