Xylon's Updated logiHSSL IP Core Seamlessly Connects Infineon AURIX Microcontrollers with AMD Adaptive SoCs and FPGAs
Xylon has announced significant architectural improvements to its popular logiHSSL Slave HSSL Controller IP core, widely used in various field applications over the past several years. The new design results in a more compact, resource-efficient IP core, enhancing its overall performance and usability.
The updated logiHSSL IP Core introduces a "reduced IP configuration," supporting one HSSL target device and one streaming data channel. Based on Xylon's experience, this configuration meets the needs of the vast majority of logiHSSL IP users. Compared to the maximum configuration, which supports up to four HSSL target and initiation devices, the reduced version saves approximately 50% of valuable programmable logic resources.
Specifically designed for AMD FPGAs and adaptive SoCs, the logiHSSL IP Core enables seamless data exchange between Infineon’s AURIX™ TC2xx, TC3xx, TC4xx microcontrollers and AMD programmable devices via the Infineon High-Speed Serial Link (HSSL). This enables system developers to combine the safety and security of AURIX microcontrollers with the versatile functionality of AMD devices. Through the HSSL, linked devices can access and control each other’s internal and connected resources.
To accelerate development in automotive and industrial applications, Xylon offers the logiHSSL-ZU FPGA HSSL Starter Kit. This comprehensive kit includes a hardware platform built from the AMD Zynq™ UltraScale+™ SoC-based ZCU104 Evaluation Kit and the Infineon AURIX Evaluation Board, along with necessary cabling and a fully functional reference hardware design.