When logiSDHC IP core device implements SDMA functionality two general scenarios are possible:
1. System RAM is accessible for logiSDHC DMA
No linker script change is necessary regarding code sections. MicroBlaze CPU and logiSDHC DMA hardware can access all application code sections placed in system RAM. A typical case is external RAM, e.g. DDR2.
2. System RAM is not accessible for logiSDHC DMA
logiSDHC DMA is unable to access any data in system RAM due to hardware limitations. Stack and heap access code sections are placed in system RAM which is not accessible for logiSDHC DMA and user application will fail to work. Therefor user must place these sections into system RAM which is accessible to logiSDHC DMA.
A typical case is LMB-BRAM. logiSDHC DMA hardware is unable to access any data in LMB-BRAM due to hardware limitations. This means that no read or write logiSDHC DMA transfer is possible. Even if external RAM is accessible through external memory controller, MicroBlaze CPU will still use LMB-BRAM for system RAM by default. In this case, LMB-BRAM is system RAM and all application code sections are placed into LMB-BRAM. Because FAT FS library together with logiSDHC driver is part of user application placed in LMB-BRAM, logiSDHC DMA hardware is unable to access code sections such as stack and heap placed in LMB-BRAM and user application will fail to work. Since MicroBlaze CPU can normally execute all code sections from LMB-BRAM, user must place stack and heap sections into RAM accessible to logiSDHC (e.g. system external RAM) making it possible for logiSDHC DMA hardware to transfer data to or from these sections. In this case user application will work properly.
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