When logiMEM_arb IP core is interfacing more than one MCB it is not doubling internal data bus, but rather interleaving memory space between each MCB’s memory space.
Idea behind interleaving memory spaces of used MCBs instead of connecting them in parallel is to avoid very wide system data buses (wider than 128-bit) and replacing them with several narrower buses. This approach allows more than one IP core to access memory simultaneously and thus optimizing system performance, latency and overall efficiency.
This is especially useful in UMA architectures comprised of many IP cores requiring memory access. Well tuned systems can achieve more than 90% of available theoretical memory bandwidth using this aproach. |