TX FIFO and RX FIFO are two separete FIFOs. Both FIFOs can be configured to be deep from 16 bytes to 1024 bytes. Depth of FIFOs is determined by generic parameter C_TX_FIFO_DEPTH and C_RX_FIFO_DEPTH. Alowed values in this generics are in between 4 and 10 and size of FIFO is then 2^C_TX_FIFO_DEPTH or 2^C_RX_FIFO_DEPTH.
RX FIFO statuses are:
- empty (RX_EMPTY) – set if receive FIFO is empty (no characters received)
- full (RX_FULL) - set if receive FIFO is full
- overflow (RX_OVFLW) - an RX FIFO overflow activates (sets) this status bit – a new character is received while the RX FIFO is full. Reading of the RX status register or software reset clears this status bit
- underrun (RX_UNDER) - set if the CPU reads from RX FIFO while it is empty. The RX FIFO pointer is decremented to 127, and software reset is required for recovery
TX FIFO statuses are:
- empty (TX_EMPTY) – set if last character is moved from transmit FIFO to shift register – TX FIFO empty and TX shift register is not
- full (TX_FULL) – set if transmit FIFO is full
- idle (TX_IDLE) – set if transmit FIFO and TX shift register are empty – all characters are sent
- overflow (TX_OVFLW) – an TX FIFO overflow activates (sets) this status bit – a CPU writes new character to the TX FIFO while the FIFO is full. Reading of the TX status register or software reset clears this status bit
All these statuses can be read from register but also some can be get from interrupts. These interupts are available:
- TX_IDLE – last character transmitted (TX FIFO and TX shift register are empty)
- TX_EMPTY – last character transmitted moved from TX FIFO to TX shift register
- RX_LEV_INT – number of characters in RX FIFO equals to the pre-programmed value in RX level register
- TX_LEV_INT – number of characters in TX FIFO equals to the pre-programmed value in TX level register
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